counters

A counter circuit is usually constructed of a number of flip-flops connected in cascade. Counters are a very widely-used component in digital circuits, and are manufactured as separate integrated circuits and also incorporated as parts of larger integrated circuits.

In this blog we will deal with asynchronous ,synchronous counter and ring counter:
1.Asynchronous counter:
Depending on the number of digits to be counted modulo N counters are configured.

Cycle	Q1	Q0	(Q1:Q0)dec
0	0	0	0
1	0	1	1
2	1	0	2
3	1	1	3
4	0	0	0

Number of flip-flops are connected in series such that the clocks of the next flip flop is triggered by the input of previous fllip flop.

design of asynchronous counter:

1.decide the no of flip-flops from the mod number from the basic equation.

modulus n=2^n

where n is the no of flipflops.

2.connect the flip flops serially as a ripple counter

3.fimd the binary number n-1

4.connect all ff outputs that are 1 at n-1 as inputs to a NAND gate.Also feed the clock pulse to the NAND gate

5.connect the NAND gate output to the preset inputs of all the flip-flops for which Q=0 at the count n-1.

  

2.synchronous counters

In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). The circuit below is a 4-bit synchronous counter. The J and K inputs of FF0 are connected to HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1. A simple way of implementing the logic for each bit of an ascending counter (which is what is depicted in the image to the right) is for each bit to toggle when all of the less significant bits are at a logic high state. For example, bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and bit 0 are all high; and so on.

Synchronous counters can also be implemented with hardware finite-state machines, which are more complex but allow for smoother, more stable transitions.

 3.ring counters

A ring counter is a circular shift register which is initiated such that only one of its flip-flops is the state one while others are in their zero states.

A ring counter is a Shift Register (a cascade connection of flip-flops) with the output of the last one connected to the input of the first, that is, in a ring. Typically, a pattern consisting of a single bit is circulated so the state repeats every n clock cycles if n flip-flops are used.

Sequential circuits-Flip flops

Sequential circuits are circuits whose output at any instant of time depends on all previous inputs.

Flip flops are sequential circuits which are configured using a set of logic gates and they can be used as a memory element. A logic gate by itself has no storage capacity but several logic gates connected together can permit storage of data.

Flip flops are also called as bistable multivibrators.

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.

1 latch:

an active high  SR latch

 

timing diagram of a simple SR latch

2.gated latches:

gated  SR latch:

Tt is sometimes useful in logic circuits to have a multivibrator which changes state only when certain conditions are met, regardless of its S and R input states. The conditional input is called the enable, and is symbolized by the letter E. 

 

When the E=0, the outputs of the two AND gates are forced to 0, regardless of the states of either S or R. Consequently, the circuit behaves as though S and R were both 0, latching the Q and not-Q outputs in their last states. Only when the enable input is activated (1) will the latch respond to the S and R inputs

3.edge triggered flip flop:

One method of enabling a multivibrator circuit is called edge triggering, where the circuit’s data inputs have control only during the time that the enable input is transitioning from one state to another.  

edge triggered SR flip flop:

Edge-triggered S-R flip-flop

The basic operation is illustrated below, along with the truth table for this type of flip-flop. The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge.

As S = 1, R = 0.  Flip-flop SETS on the rising clock edge.

Note that the S and R inputs can be changed at any time when the clock input is LOW or HIGH (except for a very short interval around the triggering transition of the clock) without affecting the output. This is illustrated in the timing diagram below:

Edge-triggered J-K flip-flop

The J-K flip-flop works very similar to S-R flip-flop.  The only difference is that this flip-flop has NO invalid state.  The outputs toggle (change to the opposite state) when both J and K inputs are HIGH.  The truth table is shown below.

 

Edge-triggered D flip-flop

The operations of a D flip-flop is much more simpler.  It has only one input addition to the clock.  It is very useful when a single data bit (0 or 1) is to be stored.  If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1.  If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0.  The truth table below summarize the operations of the positive edge-triggered D flip-flop.  As before, the negative edge-triggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge.

Applications of filp-flops:
Flip-flops have wide and extensive application in semiconductor memories,counters,shift and storage registers.
They can also be used for binary addition,serial decode,comparison and timing function.